Computer Technology Overview
Computer technology is as a branch of engineering science that deals with the systematic study of algorithmic processes, which are used to describe and transform information. Computing may encompass the design and development of software and hardware systems for a broad range of purposes – often structuring, processing and managing any kind of information – to aid in the pursuit of scientific studies, making intelligent systems, and creating and using different media for entertainment and communication.
source: computerscience.org
INVENTOR • Ken Qing Yang
ABSTRACT
APPLICATION
FEATURES & BENEFITS
Systems and methods for recovering information from NAND gates Array Memory Systems
INVENTORS • Qing Yang Weijun Xiao
ABSTRACT
A method is disclosed for recovering data associated with a damaged file stored in a NAND gate array memory. The method includes the steps of: identifying all meta data associated with the damaged file; identifying each logical block address of all identified metadata; collecting all physical block addresses associated with one of the identified logical block addresses or the identified meta data; counting in a replace table (ReplTable) a number of matches to a physical block address of the damaged file for each physical block address of the damaged file; choosing a block in a linked list that corresponds to the physical block address of the block in the linked list; and linking all chosen blocks to form a replicated file. |
APPLICATION
This can be used to recover information from a damaged flash memory such as a mobile phone or usb-drives, mainly for forensic purposes.
FEATURES AND BENEFITS
Would be great for law enforcement and other forensic accounting applications.
INTELLECTUAL PROPERTY |
Patent Number | Issue Date | Type | Country of Filing |
---|---|---|---|
US8327182 | Dec 4, 2012 | Utility | United States |
INVENTOR • Manbir Sodhi
ABSTRACT
APPLICATION
FEATURES & BENEFITS

Systems and methods for finite element based topology optimization
INVENTOR • Arun Nair, David Taggart
ABSTRACT
A method is disclosed of providing an optimal minimum mass topology for a structure based on a set of design criteria including at least one support point and at least one force to be applied to the structure. The method includes the steps of: identifying a plurality of nodes within a structure design domain, and assigning an initial density value to said plurality of nodes; conducting a finite element analysis on the nodes; determining one of a stress intensity or strain energy values for each node; ranking the nodes by relative stress intensity or strain energy values; adjusting the density value for each node; and repeating the steps of conducting a finite element analysis on said nodes, wherein the step of adjusting each density value for each node is performed according to a family of statistical distribution functions that gradually transition to a bimodal distribution wherein nodes are either fully dense or effectively void thereby providing an optimal topology.
APPLICATION
The present invention relates generally to design optimization methodologies, and relates in particular to design methodologies for developing designs of structures to support a mass with a minimum amount of material.
FEATURES AND BENEFITS
1) The invention provides a method for providing an optimal topology for a structure based on a set of design criteria including at least one support point and at least one force to be applied to the structure. The method includes the steps of identifying a plurality of nodes within a structure design domain, and assigning an initial density value to the plurality of nodes.
2) The method also includes the steps of conducting a finite element analysis on the nodes, determining a stress intensity value for each node, ranking the nodes by relative stress intensity values, and adjusting the density value for each node.
INTELLECTUAL PROPERTY |
Patent Number | Issue Date | Type | Country of Filing |
---|---|---|---|
8,335,668 | Dec 18, 2012 | Utility | United States |
Systems and Methods for On-Chip Power Management
INVENTORS • Chuen-Song Chen, Jien-Chung Lo
ABSTRACT
A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit.
APPLICATION
The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal to the integrated circuit.
FEATURES AND BENEFITS
This can significantly reduce power consumption in integrated circuits and prolong the service life cycle.
INTELLECTUAL PROPERTY |
Patent Number | Issue Date | Type | Country of Filing |
---|---|---|---|
7,902,802 | Mar 8, 2011 | Utility | United States |
System and Method for Branch Misprediction Prediction Using A Mispredicted Branch Table Having Entry Eviction Protection
INVENTOR • Resit Sendag
ABSTRACT
A system is disclosed for providing branch misprediction prediction in a microprocessor. The system includes a mispredicted branch table.
APPLICATION
The present invention generally relates to branch prediction in microprocessors, and relates in particular to systems and methods for predicting branch misprediction in microprocessors.
FEATURES AND BENEFITS
The system includes a mispredicted branch table that includes address, distance, and true/not true fields, and an index to the mispredicted branch table that is formed responsive to
1) a current mispredicted branch
2) a global history
3) a global misprediction history
4) a branch misprediction distance
Intellectual Property |
Patent Number | Issue Date | Type | Country of Filing |
---|---|---|---|
8,312,255 | Nov 13, 2012 | Utility | United States |
Cache architecture for a processing unit providing reduced power consumption in cache operation
INVENTOR • Qing Yang
ABSTRACT
A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit.
INTELLECTUAL PROPERTY |
Patent Number | Issue Date | Type | Country of Filing |
---|---|---|---|
US7966452B2 | Jun 21, 2011 | Utility | United States |